We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3342

M1.4 PAR - Mode pins and TDO do not show up in pad report for FPGAs


Keywords: mode pin, TDO, BSCAN, JTAG, M0, M1, M2, pad report,

Urgency: Standard

General Description:
When using the mode pins (MD0, MD1, MD2) and/or TDO in a design
as an I/O, the pin numbers do not show up in the pad report.


To insure that the signal is mapped to the correct pin, use the
library symbols MD0, MD1, MD2 and TDO. The pin number will not
show up in the pad report, but the signal will be mapped to the
specified pin. To verify this, EPIC can be opened and used to
view the signal to make sure it goes to the correct pin.

In M1.5, the .pad report will list Mode pins.
AR# 3342
日付 10/20/2008
ステータス アーカイブ
種類 一般