"ERROR:HDLCompiler:1318 - "<path>/xsdb_bus_controller.vhd" Line 416: Left bound value <15> of slice is out of range [7:0] of array <sl_sel_i>" has been changed to Internal"
"ERROR:Place:1145 - Unroutable Placement! A GT / BUFGCTRL clock component"
"ERROR:Pack:2310 - Too many comps of type "BUFG" found to fit this device."
"ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as "