We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 3423

96/98 DATA BOOK: RAM: Write enable pulse width following active edge of WCLK.


Keywords: Data, book, Single port, Dual port, edge triggered,
RAM, NOTE, Twps, WCLK, write clock, WE, write enable

Urgency: Standard

General Description:
The notes on pages 4-16 and 4-17 of the 9/96 Data Book and
pages 4-13 and 4-15 of the 1/98 Data Book say:

"The pulse following the active edge of WCLK (Twps in Figure
<#>) must be less than one millisecond wide. For most
applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this point
in the write cycle could result in excessive current and even cause
damage to the large devices if many CLBs are configured as
edge-triggered RAM."

These notes are misleading. They apply only to the XC4000E
devices. In the 4000EX, 4000XL, 4000XV, and subsequent
families, this problem has been resolved.


Ignore this warning if you are using 4000X parts.
AR# 3423
日付 05/31/2002
ステータス アーカイブ
種類 一般