AR# 34451

Spartan-6 FPGA Integrated Endpoint Block v1.2 rev 1 for PCI Express - Simulation never finishes when simulating a v1.2 rev 1 core generated in ISE Design Suite 11.5

説明

When I simulate a design using the Spartan-6 FPGA Integrated Endpoint Block v1.2 rev 1 for PCI Express downstream port model generated in ISE Design Suite 11.5, the simulation never completes.

ソリューション

An update is available in (Xilinx Answer 34615); download the ZIP file titled "ar34615_s6_pcie_v1_2.zip" from the Answer Record.

The ZIP file contains a file titled "pcie_clocking_v6.v[hd]" which corrects this problem. Place this file in your generated core's simulation/dsport directory.

The directory is:  /simulation/dsport/pcie_clocking_v6.v[hd]

Note that this ZIP file is cumulative and can contain fixes for other problems as described in (Xilinx Answer 34615).

Revision History
03/08/2010 - Initial Release

AR# 34451
日付 05/23/2014
ステータス アーカイブ
種類 既知の問題
デバイス
IP