An update is available in (Xilinx Answer 34615); download the ZIP file titled "ar34615_s6_pcie_v1_2.zip" from the Answer Record.
The ZIP file contains a file titled "pcie_clocking_v6.v[hd]" which corrects this problem. Place this file in your generated core's simulation/dsport directory.
The directory is: /simulation/dsport/pcie_clocking_v6.v[hd]
Note that this ZIP file is cumulative and can contain fixes for other problems as described in (Xilinx Answer 34615).
Revision History
03/08/2010 - Initial Release
| AR# 34451 | |
|---|---|
| 日付 | 05/23/2014 |
| ステータス | アーカイブ |
| 種類 | 既知の問題 |
| デバイス | |
| IP | |