AR# 34484


12.1 EDK - How can I simulate an Ethernet design with packet transmission and reception?


I would like to simulate an EDK Ethernet design for receiving and transmitting packets. But I do not have a PHY model that can be connected to the EMAC. How do I simulate this environment?


Generate a CORE Generator EMAC core with the targeted interface (MII/GMII/SGMII) and use the generated testbench in EDK.

The CORE Generator testbench stimulus provides packets at the MAC's physical interface, so within the EDK design, the user program can wait for a packet reception and send it back to the EMAC for transmission. The CORE Generator testbench then verifies the newly transmitted (looped-back) packet.

アンサー レコード リファレンス

マスター アンサー レコード

Answer Number アンサータイトル 問題の発生したバージョン 修正バージョン
34609 EDK 12.x - アンサーのリスト N/A N/A
AR# 34484
日付 06/08/2020
ステータス アクティブ
種類 一般
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