AR# 34491: SPI-4.2 v9.3 - Static Alignment could intermittently fail to go in-frame
SPI-4.2 v9.3 - Static Alignment could intermittently fail to go in-frame
An issue has been seen where the parallel ISERDES output misaligns following a core reset, resulting in the core failing to train and go in-frame.This condition can occur only when the ISERDES sees a glitch in its clock during reset and when it is configured for static alignment.This rarely happens and can be avoided if the ISERDES is reset along with the core.To exit out of this undesirable condition, re-configure the device (power-cycle).
This applies to any static alignment sink core v9.3 or earlier.
This issue is scheduled to be fixed in the next release of the core (12.1). If you have run into this issue, please contact Xilinx Technical Support.