AR# 34562

SPI-4.2 Lite v5.1 Rev2 - MMCM Mult values outside of allowable range in Virtex-6 FPGA

説明

The SPI-4.2 Lite core's clocking example designs for Virtex-6 FPGA use incorrect values for the MMCM attributes "DIVCLK_DIVIDE" and "CLKFBOUT_MULT_F" that might cause the MMCMs to operate outside of the supported range.

ソリューション

1) Sink Clock example design (pl4_lite_snk_clk.v/vhd)

For the "mmcm0" instance of MMCM (connects to RDClk clock):

Add the "DIVCLK_DIVIDE" parameter with a value of 4.
Change the value of "CLKFBOUT_MULT_F" to 8.0.

All other parameters are correct.

2) Source Clock example design (pl4_lite_src_clk.v/vhd)

For the "mmcm0" instance of MMCM (connects to SysClk clock):

Add the "DIVCLK_DIVIDE" parameter with a value of 4.
Change the value of "CLKFBOUT_MULT_F" to 8.0.

All other parameters are correct.

This issue is fixed in v5.2 of the core (available in ISE Design Suite 12.1).

AR# 34562
日付 05/23/2014
ステータス アーカイブ
種類 一般
デバイス 詳細 概略
IP