AR# 34793

12.1 PlanAhead - Synthesis fails with a netlist as top level in an RTL Project

説明

After starting in an RTL Flow in the PlanAhead tool, when I remove the top level HDL module and replace it with an EDIF top level module, XST fails.

Why is this happening?

ソリューション

If you created a project with RTL sources and try to replace the top_level with an EDIF file, synthesis fails with no messages.

If the top level source type of your design has changed, you need to create a new Netlist Project.

Improved messaging has been implemented in ISE Design Suite 12.2.

AR# 34793
日付 05/23/2014
ステータス アーカイブ
種類 既知の問題
ツール