Collisions are only possible when the packet FIFO service is included. Other cores which depend on these cores but do not use the packet FIFO service are not affected. No Xilinx EDK IP cores currently use the packet FIFO service and so are unaffected by this issue.
This issue might not be reported in simulation and could cause the core to fail in hardware. In summary, core using the read or write packet FIFO service should not be used for production in Spartan-6 until EDK 12.1.
For more information, see (Xilinx Answer 34533).
This issue is scheduled to be fixed to be fixed in EDK 12.2. A 11.5 patch will not be available before 12.1 due to ISE dependencies.
| Answer Number | アンサータイトル | 問題の発生したバージョン | 修正バージョン |
|---|---|---|---|
| 34533 | Spartan-6 FPGA ブロック RAM のデザイン アドバイザリ - アドレス空間の重複 | N/A | N/A |