AR# 3508: MAP: CY4 Symbol Errors. FPGA Express: Reading xnf or edf netlists into project.
AR# 3508
MAP: CY4 Symbol Errors. FPGA Express: Reading xnf or edf netlists into project.
説明
Keywords: FPGA Express, Foundation Express, Import, Add, CY4, Netlist, XNF
Urgency: Standard
General Description: Reading XNF netlists into FPGA Express is a legitimate process. If an XNF file is instantiated in HDL code, it can be read in and re-optimized by Express.
Unfortunately, re-optimization of XNF files can produce problems. Certain attributes (like RLOCs and other placement parameters) can be removed during the import process. In many cases this re-optimization will remove information that is needed to properly implement the design. The most common problem is with carry chains.
The following is an error message from MAP that occured after re-optimization by Express:
ERROR:x4kma:338 - CY4 symbol "pv_data_MULT_A1_USIGNED_COL_1__UN_SIGNED_G1_0__M0_UB2_CARRY_0_B_U1" (output signal=pv_data_MULT_N32X) has a CIN signal but is configured as carry-initiating mode ADD-G-F1. In this mode, the CIN pin must be left undriven. Please make sure that this ADD-G-F1 CY4 has not been improperly instantiated in the middle of a carry chain.
ERROR:x4kma:338 - CY4 symbol "pv_data_MULT_A1_USIGNED_COL_0__UN_SIGNED_G1_0__M0_UB2_CARRY_0_B_U1" (output signal=pv_data_MULT_N39O) has a CIN signal but is configured as carry-initiating mode ADD-G-F1. In this mode, the CIN pin must be left undriven. Please make sure that this ADD-G-F1 CY4 has not been improperly instantiated in the middle of a carry chain.
ソリューション
Simply instantiate the netlist and treat it as a black box. Do not read the XNF netlist into Express. Allow M1 to merge the netlists and perform any needed optimization.