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  3. AR# 3525: M1.4 Map - 5200: Map is not trimming global reset signals

AR# 3525

M1.4 Map - 5200: Map is not trimming global reset signals

説明

For the Synopsys Verilog flow, the current methodology for Verilog design creation is to connect all register reset/preset signals to both the registers and STARTUP block so that functional simulation of the reset may be performed. Upon implementation, Map should trim this signal connected to the STARTUP block however is not. This redundant routing is obviously not desired.
For more details see CR_README in the data directory.

ソリューション

A fix for this problem is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip

AR# 3525
日付 04/03/2000
ステータス アーカイブ
種類 一般