AR# 3542


Bus References in a netlist are different between Synplicity or Cadence or Mentor (xnf) and Foundation and Viewlogic (edif).


Keywords: Bus, netlist, xnf, edif, edn, synplicty, foundation, mentor, cadence, pin, mismatch, unexpanded.

Urgency: Standard

General Description:
Synplicty and others programs produces an xnf netlist with bus references like 'Data<0>' or 'Data(0)' and the edif formate is 'Data0'.
This causes a 'pin mismatch' and 'logical block is unexpanded'.



Deletting '<', '>' or '(', ')'

1. Edit the module.xnf file with an editor.

2. Search for '<' and '>' or '(' and ')' and remove them.

3. Save the module.xnf.

4. Implement the Design.


VHDL Module.

1. If module is VHDL, create each signal of the bus as an
individual pin.

2. Then in the code, create a signal or varible at the same size as the previous bus size. Then use the signal or variable name in the rest of the design, then at the end, assign the variable or signal to the individual pins.


Write xnf netlist for top level.

1. Have foundation or Viewlogic produce an xnf formate netlist (Foundation is Option -> export netlist and change type to xnf)

2. Implement the design.
AR# 3542
日付 09/17/2002
ステータス アーカイブ
種類 一般
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