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AR# 3639

V1.5, V1.4 CORE Generator - How do I get my COREGen module implementation to match the performance/speed specified in the COREGen spec sheet?


Keywords: performance, COREGen, speed, spec sheet

Urgency: Standard

General Description:
How do I get my COREGen module implementation to match the
performance specified in the COREGen spec sheet?


Performance information is not currently available for all COREGen

As for the modules that include this information,
users may find that the performance of the modules, when
processed through the Xilinx (M1)
Implementation Tools with default settings, does not match
that specified in the spec sheet for the module.

The reason for this is that the M1 MAP, Place and Route tools
emphasize design routability and minimization of processing time.
They do not aim for maximum performance by default due to the
negative impact this would have on processing time. The
default behavior is to try to get maximum routability.

To achieve maximum performance, you must apply TIMESPEC
constraints (timing specifications) on the modules that
specify the desired performance.

Please see (Xilinx Solution #1069) for basic information on
using TIMESPECs, and refer to the section on "Using
Timing Constraints" in the Xilinx Reference Guide for a
more comprehensive coverage of the subject.
AR# 3639
日付 02/08/2001
ステータス アーカイブ
タイプ ??????