AR# 3658


V1.4.0 COREGEN: Known Problems / Issues (README file / release document).


Keywords: CORE Generator v1.4.0, readme, known issues, release

Urgency: standard

General Description:
The full text of the README file shipped with the CORE Generator
v1.4.0 release is provided here for convenience's sake


README File for the CORE Generator 1.4 Software Release

Welcome to the CORE Generator 1.4 software from Xilinx!

+ Package Contents
+ Tips on Accessing Information
+ Platforms Supported
+ Architectures Supported
+ Design Entry Platforms Supported
+ Known Issues


The CORE Generator CDROM contains 3 programs, Java 1.1.3, CORE
Generator v1.4.0 and Adobe Acrobat 3.0.
Both Java 1.1.3 and the CORE Generator tool are installed by
default. On Windows platforms, you are given the option of
installing Acrobat if it cannot be found on your system. Solaris
customers can install Acrobat directly from the CD by extracting
one of the following archives found at <install_dir>/vendor/acrobat:



There are several places where you can obtain information about Xilinx
Known Issues:

+ the Known Issues section of this README file, for issues known at the
time this release went into production;
+ the online CORE Generator User Guide, which is accessible from the
HELP menu of the CORE Generator GUI. Use this resource for general
information on using the CORE Generator;
+ the Answers Search section of the Xilinx Web site.

Xilinx recommends that for the most reliable and up-to-date information
available, you should access the Answers Search page on the Xilinx
Web site. To access this page, please perform the follow steps:

1. From the Web, access Xilinx at this URL:
2. Click on Service and Support.
3. Click on Answers Search.
4. Place check marks in the boxes of the topics you would like to
5. Enter text in the search box.
6. Click Smart Search to begin search.

A CORE Generator Expert Journal page highlighting the most important
information on the CORE Generator will also be available at this site by
the end of April 1998.


+ Windows NT 4.0
+ Windows 95
+ Solaris 2.5


The following families are supported in this release: XC4000E, XC4000L,
XC4000EX, XC4000XL, XC4000XV, Spartan.


+ Viewlogic schematic
+ Foundation schematic
+ Foundation Express
+ VHDL Synthesis tools
+ Verilog Synthesis tools


+ Ref #103441: Network support. The following operation modes are
supported on Solaris systems, but not on PCs running off a Solaris
- Running the CORE Generator on a remote machine, and redirecting the
screen output to a local screen;
- Running coregen on a local machine, and accessing program files
from, or storing results to, a remote harddisk.

(Xilinx Solution #3694)

+ Warning: "The VLLINK.BAT file has a line that is longer than 254
characters. It may not execute properly on your machine."
This message applies only to Viewlogic users. The Vllink.bat file is
used to generate a Viewlogic Symbol and Simulation file for a CORE, and
will not run properly if one of the command lines is longer than 254
If you are designing with Viewlogic, you must re-install the CORE
Generator in a directory closer to the root directory. The path to the
install directory should consist of 28 characters or less, including '\'

(Addendum: This problem applies to Windows platforms only)

+ Ref #104252: Empty Error message pop-up windows.
If an error message is too long to fit into the message window, you
may see an empty pop-up window with no message. Resizing the window to
make it taller will allow you to view the message.
To permanently solve this problem, you must change your monitor
resolution to a higher level (the minimum required is 1024x768).

(Addendum: This is a problem on both Windows and Solaris platforms
and may be seen when selecting Viewlogic as the output format,
or reading in a .COE file for a FIR filter.)

(Xilinx Solution #3670)

+ Ref #103795: The CORE Generator does not warn the user before
overwriting a pre-existing CORE.
If the user is re-using the name of an existing Core, this Core
will get overwritten without any warning.

(Xilinx Solution #3696)

+ Ref #103858: "Exception occurred during event dispatching:
You may run into this error when generating a large Core (e.g.: large
PDA FIR Filters).
- Make sure that the amount of memory on your machine matches the
recommendations listed in the CORE Generator User Guide.
- If more than 64 Meg of RAM is available, increase the amount of
memory that Java has available to it by changing the -mx64m option
in the java.exe invocation to -mx128m in the "coregen.bat" file
on PC platforms, or the "coregen" script file on Solaris platforms.
On PCs, "coregen.bat" is located under <COREGEN_PATH>/bin/win;
on Solaris, "coregen" is located in <COREGEN_PATH>\bin\win.

(Xilinx Solution #3325)

+ Ref #103855: CORE Generator does not release CPU after a large
core has been generated.
This problem has been seen when generating the largest dual port
RAM and the largest FIR filter COREs.
You must exit out of the CORE Generator to release the CPU, then
restart the application to generate the next CORE.

(Xilinx Solution #3697)

+ Ref #103268: CORE Generator may core dump intermittently on Solaris.
This problem has only been seen during testing when generating
Constant Coefficient Multipliers in batch mode.
Solution: Restart the CORE Generator and regenerate the CORE.

(Addendum: This has been observed also with large cores, such
as the PDA FIR filters, as well as smaller modules. The
exception appears during "garbage collection" in AWT-Finalizer.

The problem is currently under investigation.

(See Xilinx Solution #3698)

+ Ref #103340: Timing Simulation shows XX's on the outputs of CORE
Generator COREs containing ROM/RAM.
XX's may be seen on the outputs of CORE Generator modules containing
ROM or RAM when the function generator inputs are forced to GND or
VCC (Constant Coefficient Multipliers, FIR Filters,for example).
The problem is caused by a bug in the Xilinx Mapper v1.4.
A Patch to the v1.4 Mapper will be available on the Xilinx FTP site
and from the CORE Generator Web page at:

+ Use Timespecs to meet targeted performance. The Xilinx M1 Tool is
Timing driven, and it is important to use Timespecs to specify the
performance you are trying to achieve to obtain the desired results.
Achieving the performance documented for CORE Generator COREs may
require the application of Timespecs as well.
See the Xilinx Reference Guide chapter on Using Timing Constraints
for details.

(Xilinx Solution #3639)

+ The "busy" cursor does not revert back to an arrow after CORE
generation is complete. On Windows platforms, the "busy" cursor
is an hourglass symbol, while on Solaris, it is a stopwatch.
Because the cursor does not automatically revert back to
its default appearance, this may give the impression that the
generation process is still underway.
Solution: Check the message window at the bottom of the CORE
Generator GUI to see if CORE generation has completed. Once
generation is complete, simply move your mouse to change the cursor
back to its default "arrow pointer" shape.

(Correction: This is mainly a problem on Windows platforms. The
cursor lingers on Solaris programs only if there has been a
Java error (e.g., a Java out of memory error))

(Ref #103644, #103969; Xilinx Solution #3627, #3673)

+ Error loading DataSheets in Acrobat.
Make sure that you are using Acrobat v3.0 or above, otherwise some
CORE Generator Datasheets with long file names will not be accessible.

(Mainly a problem with Acrobat v2.1.
Ref #103647, Xilinx Solution #3628)

+ Ref #103805: Viewlogic Schematic Flow: "ERROR: Could not load
schematic sheet for symbol..."
This error will be displayed for every CORE Generator module that you
have in your design when you run the Viewlogic check program. The
error is due to the fact that the BLOCKTYPE attribute on the CORE
Generator module symbol is "composite" instead of "module".
The symbol must have the "composite" property so that VSM will find
the WIR file for the COREGEN block when it generates the functional
simulation netlist for the design. You will get errors about there
not being a schematic underlying the symbol for these COREs, but
these can be ignored.

(Xilinx Solution #3079)

+ Ref #103922: ERROR starting PM. Missing LIBBASUT.DLL
This error occurs during the Viewlogic Symbol generation process when
the system is not set up properly to run the Xilinx M1 Implementation
Tools. Please refer to the Xilinx User Guide for Setup information.

(Xilinx Solution #3700)

+ Ref #104237: Datasheet "Parameter file information" tables.
Tables of "Parameter file information" in the Datasheet
for each core is provided in anticipation of support for batch mode
generation of CORE Generator modules. This capability is not supported
in the current release.

(Xilinx Solution #3702)

AR# 3658
日付 03/20/2000
ステータス アーカイブ
種類 一般
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