AR# 3663: Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
AR# 3663
Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
説明
Keywords: xx, timing simulation
Urgency: hot
General Description: Outputs of CORE Generator COREs containing ROM and/or RAM may be XX in simulation.
ソリューション
X's may be seen on the outputs of CORE Generator modules containing ROM or RAM when the function generator inputs are forced to GND or VCC (Constant Coefficient Multipliers, FIR Filters,for example).
The problem is caused by a bug in the Xilinx Mapper v1.4.
A Patch to the v1.4 Mapper is available on the Xilinx FTP site.