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AR# 3681

V1.5, V1.4 CORE Generator, LogiBLOX - What are the differences between COREGen and LogiBLOX, and which modules are generated as RPMs?


Keywords: CORE Generator, LogiBLOX, COREGen, RAM, Virtex, RLOC, RPM

Urgency: Standard

General Description:
What are the differences between the 1.5 and 1.4 versions of the LogiBLOX and
CORE Generator tools, and the functions supplied with them?



The LogiBLOX GUI is integrated into Viewlogic
and Foundation flows. The CORE Generator is
available only as a standalone tool in versions up
to the C1.5 release. In the 2.1i release, the CORE
Generator is integrated into the Foundation Project
Manager and Schematic Editor menus and can also
be invoked in standalone mode from the Windows Start Menu

LogiBLOX also allows greater flexibility in selecting which
pins will be present on a module, and whether the implementa-
tion should aim for minimum area or maximum speed.

4K, CORE Generator: Some of the 4K versions of the Coregen
modules may not give you as much flexibility in terms of pinout, but the
degree of flexibility in the Virtex cores have been enhanced.

CORE Generator cores almost always aims for maximum performance.
In some of the newer Virtex cores, you may have the option to

Another difference is that ALL cores generated with the CORE
Generator are relatively placed.

(Note that in LogiBLOX v1.4, modules that utilize carry
logic such as adders and subtracters do use RLOCs, but only
to specify the how combinational logic is mapped into the
the same CLB with carry logic, not to specify relative
placement.) This particular difference will disappear for
some additional modules in the M1.5 release, as RLOCs
will be used to constrain placement in LogiBLOX accumulator,
comparator, and counter modules as well.

RAM implementation:
- COREGEN: RAMs are 100% relatively placed, and single and
dual port RAMs of depth 64 or greater use TBUFs for
muxing/address decoding.

- LOGIBLOX: In pre-M1.5 versions of LogiBLOX, RAMs are not
relatively placed. In M1.5, the RAMs are relatively
placed, but the associated address decode muxes are not.

Also, LogiBLOX v1.5 allows the user to specify the use of
TBUFs for muxing in RAMs, if desired.

Architecture Support

LogiBLOX does not support Virtex, while the
CORE Generator will have limited support of Virtex block
RAM modules in the V1.5 release.

- XC3000A, XC5200, XC9500
Only LogiBLOX supports both XC3000A, XC5200 and XC9500
architectures, as well as all XC4000 families. COREGEN does
not support XC3000A and XC5200 FPGAs.

The CORE Generator also differs in that it also includes
datasheets for Xilinx PCI modules, and third-party
AllianceCORE modules.

1. If you need to target XC3000, XC5200, or XC9500 devices,
you must use LogiBLOX. Conversely, if you need to generate a Virtex
module, you must use the CORE Generator.

2. In general, where a given function is available in both
CORE Generator and LogiBLOX, the CORE Generator
version should give better performance
because the CORE Generator implementation is relatively
placed. Not all the LogiBLOX modules are relatively

3. Use LogiBLOX if you want to be able to control the
implementation style of your function.

4. Use CORE Generator if you wish to access new functions
which are not supported by LogiBLOX, such as:

- square root function
- multipliers
- FIR filters
- Comb filter
- other DSP related functions

5. Use CORE Generator if you wish to take advantage of the
improved performance associated with the more extensive use
of relative placement constraints (ALL CORE Generator modules
are relatively placed.)

If you do not need any of the functions supported
in the CORE Generator, you can continue to use LogiBLOX.

No new modules are planned for LogiBLOX. All new cores will be supplied
through CORE Generator. However, LogiBLOX support will continue to
support the cores and architectures it was designed for, namely, 9500,
4K, 5200 and Spartan.


X = supported
- = not supported

--------- -------------
Accumulators Standard scale by 1/2
Adders Standard Registered
Clock Dividers X -
Comparators X -
Constants X -
Counters X -
Data Registers X -
Decoders X -
Inputs/Outputs X -
Memories X -
Asynchronous RAM X Registered
Synchronous Dual Port X Registered
FIFO - Registered
Multiplexers Variable size 2-, 3-, & 4-input only
Pads -
Shift Registers X X
Simple Gates X -
Subtracters X Registered
Tristate Buffers X -
Parallel-Serial Converter Shift Register option X


COREGEN-only Functions
Time Skew Buffers - X
Sine-Cosine LUTs - X
Comb Filter - X
Registered Scaled Adder - X
Complementer - X
Integrator - X
Square Root - X
Delay Element - X

Architecture Support
XC3000A/L, XC3100A/L Yes No; not planned
XC5200 Yes No; not planned
XC4000/E/EX/XL/XV Yes Yes
Spartan Yes Yes
Virtex No limited support in v1.5
9500/XL Yes No; not planned
AR# 3681
作成日 03/24/1998
最終更新日 02/21/2001
ステータス アーカイブ
タイプ 一般