General Description: Specifying an output width of 30 bits or higher for the Square Root module may cause the behavioral model to generate the following error:
Core parameters : Output_Width = 31, Input_Width = 60. Simulation error : **Error: vhdlsim,12: Integer arithmetic overflow. Warning: vhdlsim,313: Can't display source line from file ul_utils.vhd. The file could not be located using the USE environmental/setup file variables.
This problem only affects the VHDL behavioral model for the module.
The reason why many of the modules delivered with COREGen v1.4.x are limited to bus widths of 31 or less is because of the way arithmetic operations are implemented in the VHDL behavioral models. Most models convert incoming operands from their binary (bit_vector) representations to integers, perform any necessary arithmetic using the standard set of VHDL arithmetic operators, and convert the results back to bit_vectors for expression at the output ports. Unfortunately, VHDL's integer datatype is restricted to numbers in the range -2^31 to 2^31. As a result, the above process can fail when busses with bit-widths over 31 bits contain numbers outside this range.
This problem has been fixed with the v1.4.1 patch by re-implementing the behavioral models using bit-wise arithmetic instead of integer arithmetic, since bit-wise arithmetic places no limit on bit width.