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  1. ザイリンクス - All Programmable
  2. サポート
  3. AR# 3742: A1.4/F1.4 PAR - PAR tries to insert bogus route-thru in clock IOB.

AR# 3742

A1.4/F1.4 PAR - PAR tries to insert bogus route-thru in clock IOB.

説明

PAR introduces drc errors by incorrectly trying
to use a used clock IOB site for a route-thru:

Signal REC_DISP/DISPLAY/D_CTRL/D_DRAMAD/RDCLO7 is connected
to O pin and I1 pin of the used clock IOB "CLK4X", but the
route-thru is not connected internally. This leads to DRC
warnings:

WARNING:x4kdr:20 - Blockcheck: "O" on comp (mapped physical
logic cell) "CLK4X" has a signal attatched to the pin, but
the comp is not programmed to use the pin.
WARNING:x4kdr:20 - Blockcheck: "I1" on comp (mapped physical
logic cell) "CLK4X" has a signal attatched to the pin, but
the comp is not programmed to use the pin.

ソリューション

This problem is fixed in the latest M1.4 Core Tools Patch
available on the Xilinx Download Area:

Solaris: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/core_nt17.zip


AR# 3742
日付 10/21/2008
ステータス アーカイブ
種類 一般