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AR# 38037

8.1.3i Netgen : XC9536 timesim ports are wrong

説明

In 8.1i SP3 Netgen it creates the incorrect ports for the XC9536 timesim.

ソリューション

The timesim.vhd file that is produce changes the output port to io ports. With other devices it does not do this.

For example
entity syncgen is
Port ( Fquarz : in std_logic;
PCLK_IN : in std_logic;
LVAL_OUT : out std_logic;
FVAL_OUT : out std_logic);
end syncgen;

In the timesim file you get

entity syncgen is
port (
PCLK_IN : in STD_LOGIC := 'X';
Fquarz : in STD_LOGIC := 'X';
FVAL_OUT : inout STD_LOGIC;
LVAL_OUT : inout STD_LOGIC
);
end syncgen;

This only occurs for a small number of design for the specific XC9536 device.
AR# 38037
作成日 09/15/2010
最終更新日 09/27/2010
ステータス アーカイブ
タイプ 一般