We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!


AR# 3941

NGDBUILD 1.4/1.5: basnb: 79- Pin mismatch with FPGA Express XNF instantiated in Foundation schematic


Keywords: Translate, NGDBUILD, pin mismatch, FPGA Express

Urgency: Standard

General Description:
NGDBUILD returns pin mismatch error when translating FPGA Express XNF netlist that
has been instantiated in a Foundation schematic design.

One possible cause is that not all the ports declared in the HDL source of the block are
actually used in the code. Express has realized that the ports are not being used, and
as a result, they are not included in the XNF netlist. However, the inconsistency occurs
when the ports are declared in the XSF file and do appear in the Foundation symbol.

This typically occurs when a bus is declared as a port, but not all the bits of the bus are
used in the HDL code.

This issue has been fixed in Foundation F2.1i.



The easiest solution is to remove the declarations of the unused ports in the HDL source
code. Re-implement and regenerate the symbol. Now, the pins on the symbol will match
those in the HDL.


A second method of eliminating this error is by modifying one of the files produced by
Express. Express will write an XNF (Xilinx Netlist Format) file describing the logic for the
module as well as an XSF (Xilinx Symbol Format) file to declare the pins of the module.

Open the XSF file in your favorite text editor. Let's say you have a four bit bus declared
as DATA[3:0], but you only use bits 3 and 2. Bits 1 and 0 will be trimmed out by Express,
and you will see the following in the XSF file:

BUS, DATA, 3, 2, 1, 0 <= this is what needs to be modified
PIN, DATA<3>, I, DATA<3>
PIN, DATA<2>, I, DATA<2>

You will see that the pins are correct (bits 1 and 0 are absent), but the BUS declaration
has the full range. Edit this line to remove the omitted bits:

BUS, DATA, 3, 2

Then, open the Foundation Schematic Editor and select Hierarchy -> Create Macro
Symbol from Netlist. Select the XNF file for this module and allow the existing symbol
to be overwritten.

NOTE: The XNF and XSF files are created each time the HDL macro is compiled, so if
you modify and resynthesize the HDL macro, these steps must be repeated to ensure the
macro symbol is accurate.


Another solution is to open the symbol in the Symbol Editor and modify the bus pins as
necessary. Again, this will need to be redone if the HDL macro is re-compiled, as the
symbol will be overwritten.


This error may also occur if you have imported an existing project from F1.4 or F1.3.
If there are xnf and edif netlists with the same name within the project directory, this
error may result.

Delete all *.xnf netlists that have a duplicate *.edn or *.edf netlist. Be careful not to
delete any xnf netlists that are black boxes and cannot be regenerated from HDL or
AR# 3941
日付 08/30/2001
ステータス アーカイブ
種類 一般