Inferred memory devices in process in routine jct_vhd line 18 in file 'H:/mydesign/counter.vhd'. =============================================================================== | Register Name | Type | Width | Bus | AR | AS | SR | SS | ST | =============================================================================== | COUNT_reg | Flip-flop | 8 | Y | N | N | N | N | N | ===============================================================================
signal COUNT: STD_LOGIC_VECTOR (7 downto 0); attribute sync_set_reset of RESET: signal is "true";
begin
process (CLK, RESET) begin if (CLK'event and CLK='1') then if (RESET='1') then COUNT <= "00000000"; else COUNT <= COUNT + 1; end if; end if; end process;
Inferred memory devices in process in routine jct_vhd line 18 in file 'H:/mydesign/counter.vhd'. =============================================================================== | Register Name | Type | Width | Bus | AR | AS | SR | SS | ST | =============================================================================== | COUNT_reg | Flip-flop | 8 | Y | N | N | Y | N | N | ===============================================================================