library ieee; use ieee.std_logic_1164.all; use work.all; entity top is port (vhdlinport : in std_logic; vhdloutport : out std_logic); end top; architecture arch_IncrBindMixedAssoc04_top of top is component low is port (comp_veriloginport : in std_logic; comp_verilogoutport : out std_logic); end component;
begin U1 : low port map (vhdlinport, comp_verilogoutport => vhdloutport); end ; configuration config_IncrBindMixedAssoc04_top of top is for arch_IncrBindMixedAssoc04_top for U1 : low port map (comp_veriloginport, verilogoutport => comp_verilogoutport); end for; end for; end config_IncrBindMixedAssoc04_top;