AR# 4049: MTI: Functional simulation with STARTBUF not connected properly may cause errors
AR# 4049
MTI: Functional simulation with STARTBUF not connected properly may cause errors
説明
Keywords: STARTBUF, MTI, gtsin, clkin
Urgency: Standard
General Description: When compiling a design for functional simulation using the UNISIM library, these errors may result when using the STARTBUF component:
Error Type 1 ------------ ###### use_gsr.vhd(36): U1: STARTBUF port map(GSRIN=>RESET, GSROUT=>RESET_INT); ERROR: use_gsr.vhd(36): Port "gtsin" is on entity "startbuf" but not on the component declaration. ERROR: use_gsr.vhd(36): Port "clkin" is on entity "startbuf" but not on the component declaration. ###### use_gsr.vhd(59): end XILINX; ERROR: use_gsr.vhd(59): VHDL Compiler exiting
Error Type 2 ------------ ###### use_gsr.vhd(38): U1: STARTBUF port map(GSRIN=>RESET, GSROUT=>RESET_INT); ERROR: use_gsr.vhd(38): No actual specified for gtsin. ERROR: use_gsr.vhd(38): No actual specified for clkin. -- Loading package vital_timing -- Loading entity startbuf ###### use_gsr.vhd(61): end XILINX; ERROR: use_gsr.vhd(61): VHDL Compiler exiting
ソリューション
The first error happens when the inputs CLKIN and GTSIN are not declared in the component declartion of STARTBUF.
The second error happens when the inputs CLKIN and GTSIN are not connected. To reolve this connect CLKIN and GTSIN to a dummy signal.
For example the architecture block of the design should look something like:
architecture XILINX of use_gsr is
component STARTBUF port (GSRIN: in STD_LOGIC; GTSIN: in STD_LOGIC; CLKIN: in STD_LOGIC; GSROUT: out STD_LOGIC); end component;
signal DUMMY: STD_LOGIC; signal RESET_INT: STD_LOGIC;
begin
U1: STARTBUF port map(GSRIN=>RESET, GSROUT=>RESET_INT, GTSIN=> DUMMY, CLKIN=>DUMMY );
...
end XILINX;
Note: The signal DUMMY is not sourced and will be optimized out either by the synthesis tool or by the M1 software.