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AR# 4051

M1.4 CPLD(9500): FPGA-EXPRESS - VHDL, Input to toggle control of FF inverted instead of the output.

説明

Keywords: CPLD, FPGA-EXPRESS, VHDL, FF, flip flop,
invert, toggle

Urgency: Standard

Description: Customer VHDL design in FPGA-EXPRESS
had the input of a toggle ff inverted
rather than the output. This caused
incorrect functionality on the output.

ソリューション

This problem is fixed in the latest M1.4 CPLD Tools Update
available on the Xilinx Download Area:


http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_sol9_m14.tar.Z
http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_sun9_m14.tar.Z
http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_hp9_m14.tar.Z
http://www.xilinx.com/txpatches/pub/swhelp/M1.4_alliance/cpld_nt9_m14.zip
AR# 4051
作成日 06/09/1998
最終更新日 03/02/2000
ステータス アーカイブ
タイプ 一般