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AR# 4090

ERROR:time_sim.vhd(132):Cannot assign to object with mode IN:ce. MTI timing simulation


Keywords: MTI, QuickHDL, Exemplar, timing, simulation, CE, mode, time_sim.vhd

Urgency: Standard

Problem Description:

Using Exemplar Leonardo 4.22 for synthesis, and MTI MdoelSim EE or QuickHDL
for simulation when I go to do a timing simulation with the time_sim.vhd
from the Xilinx tools and run vcom (MTI), or qvhcom (QuickHDL) I get an
error similiar to the following:

ERROR:time_sim.vhd(132): Cannot assign to object with mode IN:ce

In my code I have declared the port ce as an in std_logic. My syntheszied
design goes through the Xilinx M1 tools without any error or warnings all
the way to the bitstream.


A possible cause of this error is if the user defines a signal or port in
the design called ce, and also has at least one flop with a clock enable

This is a bug in Leonardo 4.22 in that when synthesizing the VHDL code if
the user defines a signal or port in the design called lower case ce, and
also has any flops with a clock enable in the design, will call the signal
to the flops clock enable 'CE'. This error will occur when compiling the time_sim.vhd netlist. Leonardo by default will name the signal going to
the flop clock enables uppercase CE, which is fine if the user name is
lower case ce, and will go through the Xilinx tools just fine. The problem
occurs in Modelsim which is case insensative.

This will not cause any implmentation problem with Xilinx, and will only
give errors with case insensative tools. This naming problem will be
fixed in the next release of Exemplar's software, Leonardo Spectrum.


The only workaround for now is to not use the name 'ce' for a signal or
port in the input VHDL.
AR# 4090
日付 10/06/2008
ステータス アーカイブ
タイプ 一般