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AR# 4123

V1.5 COREGEN, LOGIBLOX, VIRTEX: Virtex ROMs and SelectRAM (distributed RAM, dual port RAM, single port RAM, synchronous RAM) generation support


Keywords: coregen, rom, select, ram, distributed, virtex, synchronous
ram, dual port, single port, logiblox

Urgency: hot

General Description
Support for RLOC'd, variable size ROM and SelectRAM (distributed RAM)
for Virtex generation by the CORE Generator will not be available
until the M2.1 release timeframe. Is there a workaround in the interim
for generating Virtex distributed RAM and ROM?



There is no automated workaround for asynchronous distributed
RAMs, but you may use LogiBLOX as a workaround to generate
ROMs or single and dual port RAMs by following the following
instructions :


1. Start up LogiBLOX
2. Set the Device Family to xc4000e, xc4000ex, xc4000xl or
3. Set the Module Type to "Memories"
4. Set the memory type to SYNC_RAM, or DP_RAM depending
on whether you need Synchronous RAM, or
Dual Port RAM. (The "RAM" option for Asynchronous RAM
will not work)
5. Set the Multiplexer Style to "Normal Gates"
6. Set the option "Use RPMs" to False
7. Generate the module.
8. Incorporate the module into your design
9. Specify the desired Virtex part type when implementing the
design in the Xilinx Design Manager.

The NGC file generated using this procedure will contain
primitives which should be compatible with the Virtex
library primitives.

If a dual port RAM is generated using Logiblox, make sure that all
input and output ports are connected.


1. ROMs and RAM generated using this method will
not be RLOC'd. This may affect the performance of the
generated module.

2. RAM generated in this manner using LogiBLOX will not use
Virtex-specific MUX5 and MUX6 architectural elements.

It is not possible to retarget the COREGEN 4K distributed
RAM to Virtex because 4K RAMs generated by COREGEN are always
generated with RLOC parameters that would be incompatible with
the Virtex architecture. In addition, there is no way in COREGEN
for the user to specify how the multiplexers are implemented.


For those users requiring an RLOC'd solution, a collection of RPM'd RAM
reference designs is also being developed and will be made accessible to
customers on the WebLINX page in April 1999. This collection will be
added to incrementally on a continual basis until the M2.1i release.


Additionally, a parameterizable non-RLOC'd VHDL distributed RAM generator will
also be made available in the April 1999 timeframe.
AR# 4123
作成日 06/26/1998
最終更新日 06/28/2000
ステータス アーカイブ
タイプ 一般