ERROR:baste:263 - The LOC constraint "P7" (a IOB location) is not valid for symbol "SIG_PO" (pad signal=SIG), which is being mapped to the following site types: CLKIOB
The reason this has occurred is because the netlist dictates that the clock signal comes into the device and directly into the input of a global buffer. However, because the clock signal is not placed to an IOB with this direct access to a global buffer, this is an illegal connection.
The solution is to insert an input buffer between the pad and the global buffer.
Schematic entry ---------------
If this clock I/O has been entered in schematics, then simply insert an IBUF between the IPAD and global buffer.
HDL code --------
If the netlist has been synthesized from HDL code, the resolution will depend on the synthesis tool.
For Foundation Metamor XVHDL, the workaround is to instantiate a global buffer with the external clock signal connected to its input and the output connected to internal logic.
Please note: this issue is fixed in v1.5i or newer version of the software.