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AR# 4144

Orcad Express: Using Xilinx Alliance Series with Express

説明

Keywords: Orcad, Express, interface

Urgency: Standard

General description: The following information is provided by Orcad
as recomendations for using Orcad Express with Xilinx Alliance Series
software. For the latest information on using Orcad Express with
Xilinx implementation tools see the Orcad WEB page:

http://www.orcad.com

ソリューション

Using Xilinx Alliance Series with Express

Express/Xilinx M1 version mapping:
In general, different versions of Express are designed for use
with specific versions of the Xilinx Alliance tool set:

Xilinx Alliance Express
M1.3 v7.1x
M1.4 v7.2x

New library support:
With the release of Xilinx's Alliance Series M1.4, some of the
Xilinx component library names have been changed. Specifically,

Old library name New library name
XC4000EX/XL XC4000X
XC9000 XC9500

For legacy Express projects that target these libraries for
implementation with M1.4, you must actually create a new Express
Xilinx M1 project and select the library (with the new name) for
the list of families. After Express creates the new project, you
can then copy all .DSN and .VHD design resource and stimulus
(including test bench) files into the new project.

Also note that M1.4 has added support for two libraries previously
supported with the XACTStep tools: XC3000 and XC5200.

Command files for M1 PAR, NGDANNO, and NGD2VHDL:
In order to specify command files for the M1 utilities PAR, NGDANNO,
and NGD2VHDL, you may need to run M1 interactively. Express provides
a default command file for these utilities which may cause a switch
collision when you specify a second command file.

Xilinx ROC and oscillators: usage differences between M1.4 and M1.5:
The usages of ROC & the oscillators (OSC for 3k, OSC4 for 4k, OSC5
for 5k) in M1.4 and M1.5 are different:

For M1.4, the WIDTH parameter in ROC and the PERIOD_8M parameter in
OSC4 written into netlist by NGD2VHDL are initialized to 0 which
are not valid values and will cause Express Simulate to flag a error
and exit. According to Xilinx Alliance Series documentation, you
must provide some appropriate generic maps through the use of VHDL's
configuration. See the example below.

For M1.5, the WIDTH parameter in ROC and the PERIOD_8M parameter in
OSC4 written into netlist by NGD2VHDL are still initialized to 0.
But three command-line switches are added in NGD2VHDL:

-rpw roc_pulse_width Specify the pulse width (in ns) for ROC.
-tpw toc_pulse_width Specify the pulse width (in ns) for TOC.
-op osc_period Specify the period (in ns) for Oscillator.

(Each of the values must be a positive integer.) Use them to specify
the values used for ROC/TOC's initial pulse width and oscillators'
period. NGD2VHDL will pass these parameters using the generic maps.
For example:

ROC_NGD2VHDL: ROC generic map (WIDTH=>100 ns) port map (O=>GSR);

Q_1I11 : OSC4
generic map (
SEL_F500K => TRUE,
SEL_F490 => TRUE,
PERIOD_8M => 100 ns
)
port map (
F8M => F8M_OUT,
F500K => F500K_OUT,
F490 => F490_OUT,
F15 => NGD2VHDL_X_3_3,
F16K => NGD2VHDL_X_3_4
);

AR# 4144
作成日 08/31/2007
最終更新日 09/30/2008
ステータス アーカイブ
タイプ 一般