I cannot create TIMESPECs that include the TDO/MD1 output pad on Xilinx FPGAs. When I apply time constraints that directly feed the TDO pin, the timing report indicates the following:
"0 items analyzed, 0 timing errors detected."
AR# 4161 | |
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日付 | 05/14/2014 |
ステータス | アーカイブ |
種類 | 既知の問題 |