AR# 4173: M1.5 9500XL Fitter/Library - Clock-enable p-term not used for FDPE in Cadence and Mentor schematics.
AR# 4173
M1.5 9500XL Fitter/Library - Clock-enable p-term not used for FDPE in Cadence and Mentor schematics.
説明
Keywords: CPLD, Fitter, 9500, 9500XL, Mentor, Cadence, Concept, FDPE, CE
Urgency: Standard
General Description: In M1.5, the symbols "FDCE" and "FDPE" in the 9500/XL schematic libraries are supposed to be primitives and cause the 9500XL fitter to use the macrocell clock- enable p-term to implement the CE-input. In Cadence (Concept and Verilog) and Mentor libraries, FDPE is incorrectly configured as a macro; its CE input is implemented as gate logic on the flip-flop D-input path.
ソリューション
To implement a flip-flop with an asynchronous preset and clock-enable using the 9500XL clock- enable p-term, use a FDCE primitive in negative logic form instead of FDPE. Invert the D-input and Q-output of the FDCE, and connect your asynchronous preset to its CLR input. Also, apply the INIT property to the FDCE, indicating the opposite power-on state than you would normally specify for a FDPE.