UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4200

FPGA Express 2.x, 3.x: Constraints Editor will not allow assignment of more than 4 BUFGs

説明

Keywords: Express, clock buffers, BUFG, constraints editor

Urgency: Standard

When using Express 2.x to target an XC4000 series or Spartan device, the
Express Constraints Editor will not allow the assignment of more than four
global clock buffers to signals. The devices will allow up to eight clock
buffers to be used.

ソリューション

The solution is to instantiate all the desired clock buffers in your HDL code.

See (Xilinx Solution 3980) for examples in VHDL.
See (Xilinx Solution 3999) for examples in Verilog.
AR# 4200
作成日 07/08/1998
最終更新日 08/11/2003
ステータス アーカイブ
タイプ 一般