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AR# 4318

2.1i/1.5 VIEWLOGIC - ViewSim direct gate level schematic simulation of Virtex designs is only partially supported

説明

Keywords: gate level schematic simulation, viewsim, virtex, coregen

Urgency: Standard

General Description:
ViewLogic ViewSim direct gate level schematic simulation of Virtex designs
is only partially supported. Some components are not simulatable in the Virtex
ViewLogic library.

Please refer to (Xilinx Answer #5968) for a list of these components.

ソリューション

Customers trying to simulate a Viewlogic schematic design containing
unsimulatable library components can still simulate their Virtex designs using
VHDL or Verilog instead.

The following steps may apply to any HDL simulation tool.

Verilog Flow:

- ngdbuild -p v000 <design_name>
- ngd2ver <design_name>.ngd


VHDL Flow:

- ngdbuild -p v000 <design_name>
- ngd2vhdl <design_name>.ngd
AR# 4318
作成日 07/23/1998
最終更新日 06/13/2002
ステータス アーカイブ
タイプ 一般