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AR# 4330

Exemplar: How to force a clock signal to use an IBUF instead of the tools insert of BUFG

説明

Keywords: IBUF, BUFG, clock, buffer, normal, I/O

Urgency: Standard

General Description:

My design has multiple clocks and I want to force one clock to use a
non-clock buffer, an IBUF, instead of the BUFG. Using the Leonardo GUI and
the default options, I have instantiated an IBUF on the clock signal that
goes to the clock of a flip flop. The tools automatically replaces the IBUF
with a BUFG. How can I force the IBUF to be used?

ソリューション

1

By default the Leoanardo GUI will force clock signals to global buffer when
the resources are available. If the design has multiple clocks then the best
way to get around this is to turn off global buffer insertion, then use the
buffer_sig attribute to push BUFG's onto the desired signals, if needed. By
doing this the user will not have to instantiate any BUFG components, and
as long as "chip" options is used in optimize the IBUF's will be auto-inserted..

Do the following:

For LeonardoSpectrum:
-------------------------------------

1) In the Technology --> Advanced Settings Tab DESELECT the option
'Add Clock Buffer'

2) Load the library

3) Read the HDL files.

4) After 'Read' use the buffer_sig to get BUFG's on the desired signals, if needed.

set_attribute -port clk1 -name buffer_sig -value BUFG
set_attribute -port clk2 -name buffer_sig -value BUFG

5) Optimize the design..

6) Verify the proper buffers were used on the proper signal by using the
'View Schematic' feature.

7) write out the Edif netlist.

2

For Leonardo 4.2.2:
--------------------------------
Do the following:

1) load the library.

2) After 'Read' use the buffer_sig to get BUFG's on the desired signals, if needed.

set_attribute -port clk1 -name buffer_sig -value BUFG
set_attribute -port clk2 -name buffer_sig -value BUFG

3) In Optimize->Advanced DESELECT the option to 'Map to Clock/Global Buffers'
This will prevent Exemplar from changing an IBUFG to a BUFG, and will also
prevent an auto-insertion of a BUFG.

4) Verify the proper buffers were used on the proper signal by using the
'View Schematic' feature.

5) write out the Edif netlist.
AR# 4330
作成日 07/27/1998
最終更新日 04/24/2007
ステータス アーカイブ
タイプ 一般