Synopsys Design Compiler users may encounter the following errors during NGDBUILD
ERROR:basnb:79 - Pin mismatch between block "U3", TYPE="ramblock", and file "/home/grover2/ramblock.ngo" at pin "spo<7:0>(0)". Please make sure that all pins on the instantiated component match pins in the lower-level design block. (Pin-name matching is case-insensitive.)
ERROR:basnu:93 - logical block "U3" of type "ramblock" is unexpanded
FPGA Compiler users generally do not receive these errors due to the fact that FPGA Compiler generally writes out SXNF format netlists.
The general cause of these errors is an incorrect .synopsys_dc.setup file. Ensure that the variable "edifout_no_array = true" is in the .synopsys_dc.setup file. This variable will break the buses into bits in the EDIF implementation netlist.
Xilinx suggests all users use the Synopsys setup files in the $XILINX/synopsys/examples directory.