UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4347

Foundation F1.5 Simulation, CORE Generator - Must create a Foundation Schematic Symbol in COREGen to Functionally Simulate

説明

Keywords: CORE Generator, COREGen, simulate, functional, simulation, HDL, VHDL, Verilog

Urgency: Standard

General Description:
In a design that contains CORE Generator components, you must create a Foundation Schematic Symbol in the CORE Generator GUI to be able to run Functional Simulation from within Foundation. This includes VHDL or Verilog designs.

ソリューション

The Foundation simulation model is created when you choose the Foundation Schematic Symbol option in CORE Generator. Even though this file is not required to be able to implement the design, it is required if you wish to perform Functional Simulation in Foundation BEFORE the design is implemented with the Implementation Tools.

In the CORE Generator Options dialog, be sure that the "Foundation Schematic Symbol" output format is selected.
AR# 4347
作成日 07/28/1998
最終更新日 06/14/2001
ステータス アーカイブ
タイプ 一般