UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4393

Mentor Graphics, PLD_DA - How to enter a TIG constraint

説明

This solution describes the method to place a TIG (Timing Ignore) property on a Mentor Design Architect schematic net in order to tell the M1 tools to ignore this path for timing driven placement and routing.

ソリューション

To add a TIG constraint to a net: 

 

1. Select the net. Make sure the vertex where the output of a symbol connects to the net. Be sure you have selected only that vertex; a single star should appear at that location. 

 

2. Press the right mouse button. The Net popup menu will appear if you have selected a net or a pin. 

 

3. Select the Properties -> Add -> Add Single Property command from the popup menu. The Add Property dialog box appears. 

 

4. In the Property Name box, type TIG. 

 

5. If the TIG property is to be applied globally to the design, leave the Property Value box empty. Otherwise, type in the TS identifier to be ignored in the Property Value box. 

 

6. Select String in the Property Type field and Select OK.

AR# 4393
作成日 08/21/2007
最終更新日 05/14/2014
ステータス アーカイブ
タイプ 一般