AR# 4415: PPR WARNING 7028: How to set Flagblk CLB_Disable_SR_Q on Flops in Xdelay
PPR WARNING 7028: How to set Flagblk CLB_Disable_SR_Q on Flops in Xdelay
Keywords: xdelay, asynchronous, set, reset, path.
General Description: If your design has flip-flops with asynchronous set/reset, you might get the following warning from PPR:
*** PPR: WARNING 7028: The design has flip-flops with asynchronous set/reset controls (PRE/SD or CLR/RD pins). When PPR analyzes design timing, it does not trace paths through the asynchronous set/reset input and on through the Q output.
If you want PPR to control the delay on paths through asynchronous set/reset pins, you must split the delay requirement into two segments: one ending at the set/reset input, and the other beginning at the flip-flop output. If you want PPR not to analyze paths that lead to asynchronousset/reset pins, attach an IGNORE specification to the pin(s) or signal(s).
By default, XDelay reports all paths through asynchronous set/reset pins. To prevent XDelay from showing these paths, use FlagBlk CLB_Disable_SR_Q on the appropriate flip-flops.
How do to set Flagblk on in XDELAY?
1- Start Xdelay. 2- Load the design_name.lca file. 3- Click on Timing Menu and select Flagblk. 4- It now lists all of the available flags. Select CLB_Disable_SR_Q 5- It will now list all of the flops in the design. You can select as many as you want or you can select them all. Then close. 6- Click on Timing Menu and select Save Template. It will prompt you for a name and click ok. 7- Then run the analysis in xdelay. To use this flag in the future simply load the template before analyzing.