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AR# 4426

M1.4: TRCE: Path through asynchronous ram we is traced

説明

Description: Design contains a RAM16X1. The designer constraints several paths in the design with the following constraint.

TIMESPEC TS_01=FROM:PAD:TO:PAD:20;

There are five PAD to PAD paths. Four starting at each input PADs through the address pins on the RAM to the output PAD. The fifth path is from the input PAD through the WE pin on RAM to the output PAD.

When you run TRCE/Timing Analyzer each of these paths is reported and analyzed. If you add the following constraint.

TIMESPEC TS_02=FROM:RAM:TO:PAD:20;

The fifth path through the WE pin is no longer reported.

ソリューション

This is scheduled to be fixed in the next software release.

AR# 4426
作成日 08/11/1998
最終更新日 01/18/2010
ステータス アーカイブ
タイプ 一般