General Description:
In the TPTHRU dialog, the net A_EQ_B doesn't show up,
but view the design in FPGA Editor, the net is listed.
The net is connected to the CLK_EN pin (clock enable),
which is not listed under All Nets
This will be fixed in a future release of the software or
service pack.
| AR# 4461 | |
|---|---|
| 日付 | 01/18/2010 |
| ステータス | アーカイブ |
| 種類 | 一般 |