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AR# 4543

V1.5, V1.4 CORE Generator - Only the LSBs of a cascade mode SDA FIR output are defined in a Verilog behavioral simulation.


Keywords: CORE Generator, COREGen, Verilog, behavioral simulation,
cascade mode, SDA

Urgency: Hot

General Description:
In a Verilog behavioral simulation of the CORE Generator SDA FIR filter in
cascade mode, only the lower 24 bits of a 32-bit output are defined. All
upper bits are stuck at X.


The problem is that the "full_result_width" parameter is
declared with a value of 24, which effectively limits the
precision with which the output can be reported.

The fix is to extend the bus-width parameter value to 100 bits
in the SDA FIR Verilog behavioral model:

The line that needs to be modified is preceded by this comment:

//Start of constant declarations - do not overload

The parameter, "full_result_width", on line 77 needs to be changed from
24 to 100:

parameter full_result_width = 100;

This problem is only seen in the Verilog version of the
behavioral model and has been fixed in the 1.5.2
CORE Generator patch.
AR# 4543
日付 02/15/2001
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