AR# 45447

説明

ソリューション

この問題は、qdr_rld_mc_phy モジュールにおける PO_OCLK_DELAY パラメーターの設定に 666.67MHz 未満の周波数の追加割り当てがないことが原因で発生します。 

localparam integer PO_OCLK_DELAY = (SIMULATION == "TRUE") ? MC_OCLK_DELAY :

(CLK_PERIOD <= 938) ? 23 :
(CLK_PERIOD <= 1072) ? 24 :
(CLK_PERIOD <= 1250) ? 25 :
(CLK_PERIOD <= 1500) ? 26 : 27;

//*******************************************************************************************************************
// OCLK_DELAYED 90 degree phase shift calculations
//*******************************************************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz and 1.25 for Mem_RefClk > 300 MHz

localparam PO_OCLKDELAY_INV = ((SIMULATION == "FALSE" && CLK_PERIOD > 2500) || CLK_PERIOD>= 3333) ? "FALSE" : "TRUE";

//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, DIV4: MemRefClk < 200 MHz

localparam PHY_FREQ_REF_MODE = CLK_PERIOD > 5000 ? "DIV4" : CLK_PERIOD > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_FREQ_REF_MODE == "DIV4" ? 4 : PHY_FREQ_REF_MODE == "DIV2" ? 2 : 1);

//FreqRefClk (MHz) is 1,2,4 times faster than MemRefClk

localparam real FREQ_REF_MHZ = 1.0/((CLK_PERIOD/FREQ_REF_DIV/1000.0) / 1000) ;
localparam real MEM_REF_MHZ = 1.0/((CLK_PERIOD/1000.0) / 1000) ;

// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output

localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/CLK_PERIOD; // Fraction of MemRefClk

// Whether OCLK_DELAY output comes inverted or not

localparam real HALF_CYCLE_DELAY = 0.5 * (PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); //Fraction of MemRefClk

// Phaser-Out Stage3 Tap delay for 90 deg shift. Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/63/FREQ_REF_DIV;
// Equation: INT_DELAY + HALF_CYCLE_DELAY + TAP_DELAY = 0.25 or 1.25 MemRefClk cycles

localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV;

//localparam integer PO_OCLK_DELAY = MC_OCLK_DELAY; // MC_OCLK_DELAY + 0.5;

localparam integer PO_OCLK_DELAY
= (SIMULATION == "TRUE") ? MC_OCLK_DELAY :
(CLK_PERIOD > 2500) ? 8 :
(CLK_PERIOD <= 938) ? 23 :
(CLK_PERIOD <= 1072) ? 24 :
(CLK_PERIOD <= 1250) ? 25 :
(CLK_PERIOD <= 1500) ? 26 : 27;

//*******************************************************************************************************************
// OCLK_DELAYED 90 degree phase shift calculations
//*******************************************************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = ((SIMULATION == "FALSE" && CLK_PERIOD > 2500) || CLK_PERIOD>= 3333) ? "FALSE" : "TRUE";

//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400, DIV4: MemRefClk < 200 MHz
localparam PHY_FREQ_REF_MODE = CLK_PERIOD > 5000 ? "DIV4" : CLK_PERIOD > 2500 ? "DIV2": "NONE";

localparam FREQ_REF_DIV = (PHY_FREQ_REF_MODE == "DIV4" ? 4 : PHY_FREQ_REF_MODE == "DIV2" ? 2 : 1);

//FreqRefClk (MHz) is 1,2,4 times faster than MemRefClk
localparam real FREQ_REF_MHZ = 1.0/((CLK_PERIOD/FREQ_REF_DIV/1000.0) / 1000) ;
localparam real MEM_REF_MHZ = 1.0/((CLK_PERIOD/1000.0) / 1000) ;

// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/CLK_PERIOD; // Fraction of MemRefClk

// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5 * (PO_OCLKDELAY_INV == "TRUE" ? 1 : 0); //Fraction of MemRefClk

// Phaser-Out Stage3 Tap delay for 90 deg shift. Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/63/FREQ_REF_DIV;

// Equation: INT_DELAY + HALF_CYCLE_DELAY + TAP_DELAY = 0.25 or 1.25 MemRefClk cycles
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) - (INT_DELAY + HALF_CYCLE_DELAY)) * 63 * FREQ_REF_DIV;
//localparam integer PO_OCLK_DELAY = MC_OCLK_DELAY; // MC_OCLK_DELAY + 0.5;

localparam integer PO_OCLK_DELAY
= (SIMULATION == "TRUE") ? MC_OCLK_DELAY :
(CLK_PERIOD > 2500) ? 8 : 1;

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