This Solution record describes how to specify the INIT attribute on instantiated ROM/RAM primitives in a Synopsys Design Compiler Verilog or VHDL design. The INIT attribute specifies the initialized value of the component and is required on the ROM primitives (ROM16X1, ROM32X1) if instantiated in the design.
ソリューション
Before specifying the set_attribute command to initialize the ROM/RAM components, the following line needs to be added to the .synopsys_dc.setup file if it is not already there:
where <instance_name> is replaced by the instance name given to the instantiated ROM/RAM primitive and <value> is the hex value desired to be placed on that component.
Repeat this command for each ROM/RAM component you wish to initialize.