UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4624

M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of an XC9500 FDCP

説明

Description: The path through the asynchronous preset or clear of

an FDCP in the XC9500 family cannot be analysed using the timing

analyser. The path up to the preset or clear *is* measurable, but not

the path through the flop from the pre/clr to the output.

ソリューション

The path delay may be calculated manually using the XC9500 timing

model:

tin + tptsr + t aoi + tout

This would be from a pad, through a buffer to the preset/clear, through

the flop, through the output buffer and to the opad.

AR# 4624
作成日 08/31/2007
最終更新日 01/18/2010
ステータス アーカイブ
タイプ 一般