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AR# 4667

8.1i CPLDFit - Output in design becomes bidirectional (I/O) in after implementation

説明

Keyword: 7.1i, 6.3i, 6.2i, 6.1i, bidirectional, tristate, output, hitop, xnf  

 

A pin that is an output in the design turns into a bi-directional pin (I/O) after fitting. Is this a bug?

ソリューション

This should only happen with the XC9500 family. This does not apply for XC9500XL/XV or CoolRunner devices. 

 

This is the result of the CPLDFit switch labelled "Use Pin Feedback". 

 

This option tries to use the signal from the pin, rather than the signal going to the universal interconnect matrix (uim) feedback from the original macrocell. This option saves the user a couple of nanoseconds and makes the design faster. 

 

The software began using a signal that was originally just an OUTPUT and converted the output into an I/O. The end result is that the tPD may be a few ns faster. Because the pin is used anyway, there is no harm in converting the pin to an I/O. However, this might cause problems with post-route simulations, where the pin format now results in a mismatch. 

 

If this is not desired, turn off the setting "Use Pin Feedback".

AR# 4667
作成日 08/21/2007
最終更新日 05/14/2014
ステータス アーカイブ
タイプ 一般