AR# 47280: Virtex-6 Integrated Block for PCI Express v2.5 - Timing fails due to missing Block RAM Placement (LOC) Constraints in the Example Design UCF
INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_mem64" LOC = RAMB36_X5Y12; INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_io_mem" LOC = RAMB36_X5Y13; INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_mem_erom" LOC = RAMB36_X5Y14; INST "app/PIO/PIO_EP/EP_MEM/EP_MEM/ep_mem32" LOC = RAMB36_X5Y15;
INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[1].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y0; INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[1].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y1; INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_tx/brams[0].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y2; INST "core/pcie_2_0_i/pcie_bram_i/pcie_brams_rx/brams[0].ram/use_ramb36.ramb36" LOC = RAMB36_X9Y3;