We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 4831

COREGEN: Output of Delay Element module does not change in simulation if CE is unconnected


General Description: 
Output of COREGEN Delay Element module does not change in  


The Delay Element does not float its CE input to VCC if left  
unconnected. The signal tied to this pin is used internally  
to activate the WE pin of the RAM used to store the input  
to the Delay Element.  
CE should always be tied either to VCC or to a control signal  
whose logic level is defined--it will not respond to a clock  
input unless its CE pin is driven to a logic 1 level.
AR# 4831
日付 05/14/2014
ステータス アーカイブ
種類 一般