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AR# 4874

M1.5 LOGIBLOX - Generates empty Verilog .v simulation models for IN, OUT, and INVERT modules.

説明

Keywords: LogiBLOX, in, out, invert, empty, Verilog

Urgency: Hot

General Description:
Verilog simulation models generated by LogiBLOX in the M1.5
release for IN and OUT modules are empty.

ソリューション

LogiBLOX calls NGD2VER to generate the Verilog functional simulation
models for the modules it generates. The problem with the empty
Verilog simulation models for IN, OUT and INVERT modules is
caused by a bug in NGDPREP, a subprogram called by NGD2VER.

The problem can be corrected by disabling the optimizer; to do this,
set the XIL_PP_OPTIMIZE environment variable:

UNIX:
setenv XIL_PP_OPTIMIZE ""

Windows:
set XIL_PP_OPTIMIZE=0
AR# 4874
作成日 08/31/2007
最終更新日 02/15/2001
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