UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. ザイリンクス - All Programmable
  2. サポート
  3. AR# 4913: 2.1i CORE Generator - Sample COREGEN .COE coefficient files for a FIR filter, Distributed RAM, Distributed ROM, and Block RAM

AR# 4913

2.1i CORE Generator - Sample COREGEN .COE coefficient files for a FIR filter, Distributed RAM, Distributed ROM, and Block RAM

説明


Keyword: COREGen, CORE Generator, ROM, RAM, FIR, Filter, PDA, SDA, 2.1i







General Description:

The following are sample CORE Generator coefficient (.coe) files for FIR Filters, Distributed ROM and RAM, and Virtex Block Memory.



The sample COE files may also be found in your CORE Generator installation under the $XILINX\coregen\data directory.

ソリューション


SDA FIR Filter:



Component_Name=sdafir;

Number_Of_Taps=6;

Radix=10;

Input_Width=10;

Output_Width=24;

Coefficient_Width=11;

Impulse_Response_Symmetry = false;

CoefData= -1,18,122,418,-40,3;



Here is a brief explanation of the keywords in the coefficient file:



Component_name: Declares the name of the component.



Number_of_taps: Specifies the number of taps.



Radix: Specifies the base of the coefficient.

(Radix=10 indicates that the coefficients are in base 10 (decimal) format;

Radix=16 indicates that the coefficient is in hexadecimal.)



Input_width: Specifies the input data width.



Output_width: Specifies the output data width.



Coefficient_width: Specifies the output width.



Impulse_Response_Symmetry: Specifies the symmetry of the filter. "TRUE" indicates that the filter coefficients are symmetrical; "FALSE" means they are asymmetrical.



Coef_Data: Value of the coefficients



For more information, please refer to the specification sheets for the FIR filters.



Distributed RAM with hexadecimal data:



Component_Name=ram16x12;

Data_Width = 12;

Address_Width = 4;

Depth = 16;

Radix = 16;

memdata=346,EDA,0D6,F91,079,FC8,053,FE2,03C,FF2,02D,FFB,022,002,

01A,005;



For more information, please refer to the online specification sheet for Distributed RAMs in CORE Generator.



Distributed RAM with decimal data:



Component_Name=rom32x8;

Data_Width = 8;

Address_Width = 5;

Depth = 32;

Radix = 10;

memdata=127,127,127,127,127,126,126,126,125,125,125,4,3,2,0,-1,-2,

-4,-5,-6,-8,-9,-11,-12,-13,-38,-39,-41,-42,-44,-45,-128;



Dual-Port Block RAM:



Component_Name=v_dpbram;

Depth_A = 4096;

Data_Width_A = 16;

Depth_B = 1024;

Data_Width_B = 64;

Radix = 2;

Default_Data = 10101010;

MEMORY_INITIALIZATION_VECTOR=

1111111111111110,

1111111111111101,

1111111111111011,

1111111111110111;



For more information, please refer to the online specification sheet for Block RAMs in CORE Generator.



Single-Port Block RAM:



Component_Name = v_spbram;

Depth = 256;

Data_Width = 32;

Radix = 16;

Default_Data = FFF;

MEMORY_INITIALIZATION_VECTOR = FF0,F0F,0FF,FF4,F4F,4FF,FF8,F8F,8FF;





For more information, please refer to the online specification sheet for Block RAMs in CORE Generator.
AR# 4913
日付 02/06/2012
ステータス アーカイブ
種類 一般
このページをブックマークに追加