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AR# 4945

Synopsys FPGA/Design Compiler: How to use the TRANSLATE_OFF and TRANSLATE_ON pragmas


Keywords: Translate_off, Translate_on, FPGA Compiler,
Design Compiler, pragma, Synopsys, UNISIM

Urgency: Standard

General Description:

It is sometimes useful to use the Synopsys TRANSLATE_OFF and
TRANSLATE_ON pragmas in a VHDL design in order to be able to not
specify the UNISIM libraries for synthesis but have them for

This solution record describes what needs to be done to be able to
properly use these pragmas with Synopsys FPGA Compiler or Design


To make these pragmas effective a Synopsys variable called
hdlin_translate_off_skip_text must be set to true (this variable is
defaultly false). The easiest way to do this is to add the
following line to your .synopsys_dc.setup file:

hdlin_translate_off_skip_text = true

With this variable set to true, all text within the pragmas will be
ignored during synthesis.

These pragmas can be specified on one of two ways.

Method 1:

-- SYNOPSYS translate_off

LIBRARY unisim;
use unisim.vcomponents.all;

-- SYNOPSYS translate_on

Method 2:

-- PRAGMA translate_off

LIBRARY unisim;
use unisim.vcomponents.all;

-- PRAGMA translate_on
AR# 4945
日付 04/27/2007
ステータス アーカイブ
タイプ 一般