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AR# 4981

FPGA Express: How to access Carry-In when building arithmetic functions

説明

Keywords: Express, Foundation, carry, add, subtract, VHDL, Verilog

Urgency: Standard

General Description:
When creating an adder or subractor with a single bit carry-in signal, one
cannot simply code A + B + Cin (where A and B are N bits wide, and Cin is a
single bit carry in signal), as this will produce two N-bit counters.

Use the following examples to infer a carry-in signal for the carry chain
built by FPGA Express.

ソリューション

1

--VHDL Example
--'dummy' signal will be removed

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity add_vhd is
port(a, b : in std_logic_vector(15 downto 0);
cin : in std_logic;
sum : out std_logic_vector(15 downto 0));
end add_vhd;

architecture behav of add_vhd is
signal dummy : std_logic_vector(16 downto 0);
begin
dummy <= (a & cin) + (b & cin);
sum <= dummy(16 downto 0);
end behav;

2

//Verilog Example
//'dummy' signal will be removed

module add_v (a, b, cin, sum);
input [15:0] a, b;
input cin;
output [15:0] sum;

wire dummy;

assign {sum, dummy} = {a, cin} + {b, cin};

endmodule
AR# 4981
作成日 11/04/1998
最終更新日 08/11/2003
ステータス アーカイブ
タイプ 一般